The present invention relates to communications between processes in a multiprocessor system, and more particularly relates to providing a heuristics algorithm for calculating delays in the implementation of initiative passing in an input/output (I/O) operation without interrupt overhead.
U.S. Pat. No. 4,447,873 issued May 8, 1984 to Price et al. for INPUT-OUTPUT BUFFERS FOR A DIGITAL SIGNAL PROCESSING SYSTEM discloses buffer interfaces wherein a storage controller which generates control signals indicating when it is in a condition to receive a vector of data words from the storage controller, whereon the storage controller transfers a vector of data to the input buffer.
U.S. Pat. No. 5,671,365 issued Sep. 23, 1997 to Binford et al. for I/O SYSTEM FOR REDUCING MAIN PROCESSOR OVERHEAD IN INITIATING I/O REQUESTS AND SERVICING I/O COMPLETION EVENTS, and U.S. Pat. No. 5,875,343 issued Feb. 23, 1999 to Binford et al. for EMPLOYING REQUEST QUEUES AND COMPLETION QUEUES BETWEEN MAIN PROCESSORS AND I/O PROCESSORS WHEREIN A MAIN PROCESSOR IS INTERRUPTED WHEN A CERTAIN NUMBER OF COMPLETION MESSAGES ARE PRESENT IN ITS COMPLETION QUEUE disclose an apparatus wherein I/O requests are queued in a memory shared by one or more main processing units and one or more I/O processors. Each I/O processor is associated with a queue, and each main processing unit is associated with a queue shared with the I/O processors. Each I/O processor may continue processing queued I/O requests after completing processing an earlier request. A threshold value indicates the minimum number of completed I/O requests required before an interrupt request is generated to the main processing unit. Many events are batched together under one interruption.
U.S. Pat. No. 5,771,387 issued Jun. 23,1998 to Young et al. for METHOD AND APPARATUS FOR INTERRUPTING A PROCESSOR BY A PCI PERIPHERAL ACROSS AN HIERARCHY OF PCI BUSES discloses a hierarchy of PCI buses for facilitating PCI agents coupled to the lower lever PCI buses to interrupt a processor during operation.
U.S. Pat. No. 6,032,217 issued Feb. 29, 2000 to Arnott for METHOD FOR RECONFIGURING CONTAINERS WITHOUT SHUTTING DOWN THE SYSTEM AND WITH MINIMAL INTERRUPTION TO ON-LINE PROCESSING discloses a method for concurrently reorganizing a disk file system while continuing to process I/O requests. The method includes stopping processing of new I/O requests by queuing them within the system, finishing processing I/O requests in progress, performing the reorganization, and then processing the queue of stored I/O requests before finally resuming normal operation.
U.S. Pat. No. 6,085,277 issued Jul. 4, 2000 to Nordstrom et al. for INTERRUPT AND MESSAGE BATCHING APPARATUS AND METHOD discloses an interrupt and batching apparatus for batching interrupt processing for many events together.
An apparatus, method and program product for use with a data processing system having a processor handling an J/O request in an I/O operation, main storage controlled by said processor for storing data, one or more I/O devices for sending data to or receiving data from said main storage in the I/O operation, and a summary register for registering I/O requests by any one or more of said devices. The apparatus includes a dispatcher for polling said summary register to determine if an I/O request is outstanding. A program in the dispatcher calculates a delay value responsive to the workload of the processor in handling I/O requests. An adapter between the device and the processor drives an interrupt of the processor if the calculated time delay is exceeded between completing I/O requests.
Certain workloads may incur undesirable latency using a given time delay to determine when to drive an interrupt due to a design point to not generate interrupts until a subsequent completion occurs, after the delay value has been exceeded, for example, if such a subsequent completion never occurs. In this case, a last resort timer is required for the pending completion notice(s) to be processed. Given that this timer is relatively infrequent relative to the processing of an I/O interrupt, undesirable latency will be incurred.
It is thus an object of the present invention to provide shorter I/O completion latencies for workloads comprised of a single user, request/response application which is the only application running on a target Operating System (OS) image.
It is another object of the present invention to provide workload heuristics used to detect I/O completion patterns and take the appropriate action. The action taken would be to dynamically change the OS specified delay value to/from zero. Specifying a delay value of zero tells the device to generate an interrupt upon every I/O completion.
It is another object of the invention which, when the heuristics have determined that the target delay interval is consistently not being met, the OS would change the delay value to zero.
It is another object of the invention which, when the target interval is consistently being met, the OS would change the delay value to nonzero, thereby allowing interrupts to be amortized across multiple completions.
It is another object of the invention to provide a heuristics algorithm which includes maintaining the average delay that was incurred from the time a global summary byte is set by an adapter, to the time it is reset by the dispatcher. This average would be calculated every X number of global summary byte resets. At that time, a decision would be made as to whether or not the target interval, on average, was being met, so the appropriate action could be taken.
It is another object of the invention to provide the keeping of additional information to both avoid thrashing between zero and nonzero values, and to postpone probe activity (i.e. change from zero to nonzero delay values) when previous attempts have consistently failed.